Project/VHDL - Revision history

Danny w: /* Components */

2016-01-01T12:41:39Z

Components

← Older revision		Revision as of 15:41, 1 January 2016
Line 164:		Line 164:
	This is a representation of the PWM output design in an actual device. 196 is the input of our PWM value. All bits of count_internal are shown, and indeed forms a counter that counts upwards. It's shown as a line representing the value of count_internal, clearly a sawtooth pattern. At the bottom is our PWM output. It's most of the time high, and also a small part low. For 196 of the 255 parts, it's high, and the rest low signal level.		This is a representation of the PWM output design in an actual device. 196 is the input of our PWM value. All bits of count_internal are shown, and indeed forms a counter that counts upwards. It's shown as a line representing the value of count_internal, clearly a sawtooth pattern. At the bottom is our PWM output. It's most of the time high, and also a small part low. For 196 of the 255 parts, it's high, and the rest low signal level.

	The way this actually works is as follows: The compiler program implements, besides our own PWM design, also the design of a logic analyzer. The data from this is sent over the programming port to the computer. The signals on our picture actually represents the signals inside our device. This ~~actually~~ is a very helpful tool to debug our designs. The FPGA in this case is running at full speed, while we can monitor all the signal levels we want inside. In Altera terms, this is called a "Signal Tap". The data collected from our selected lines is stored in the device's internal memory blocks and sent over the JTAG programming port.		The way this actually works is as follows: The compiler program implements, besides our own PWM design, also the design of a logic analyzer. The data from this is sent over the programming port to the computer. The signals on our picture actually represents the signals inside our device. This is a very helpful tool to debug our designs. The FPGA in this case is running at full speed, with real-life signals, while we can monitor all the signal levels we want inside. In Altera terms, this is called a "Signal Tap". The data collected from our selected lines is stored in the device's internal memory blocks and sent over the JTAG programming port.

	== Shifting <s>reality</s> registers ==		== Shifting <s>reality</s> registers ==

Danny w: /* Components */

2016-01-01T12:38:49Z

Components

← Older revision		Revision as of 15:38, 1 January 2016
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	We start the architecture with our component instantiation. We can "map" the signals and generics inside our component to internal or external signals in our PWM output entity, and fixed values like the binary '0' for our reset signal. We do not want our counter to reset to its 0-state. Instead, the counter will wrap around if we count further than the bit capability. This will represent the PWM cycle in our design. If the current counter value is lower than the desired one in the <code>pwm_value</code> input, the output of our design will be high. Otherwise, the output will be low. For our 8 bit (0 to 255 value) PWM design, a PWM value of 63 will mean a quarter of the period time high, and three quarters of the period time low output value.		We start the architecture with our component instantiation. We can "map" the signals and generics inside our component to internal or external signals in our PWM output entity, and fixed values like the binary '0' for our reset signal. We do not want our counter to reset to its 0-state. Instead, the counter will wrap around if we count further than the bit capability. This will represent the PWM cycle in our design. If the current counter value is lower than the desired one in the <code>pwm_value</code> input, the output of our design will be high. Otherwise, the output will be low. For our 8 bit (0 to 255 value) PWM design, a PWM value of 63 will mean a quarter of the period time high, and three quarters of the period time low output value.

			[[File:pwm_output.png]]

			This is a representation of the PWM output design in an actual device. 196 is the input of our PWM value. All bits of count_internal are shown, and indeed forms a counter that counts upwards. It's shown as a line representing the value of count_internal, clearly a sawtooth pattern. At the bottom is our PWM output. It's most of the time high, and also a small part low. For 196 of the 255 parts, it's high, and the rest low signal level.

			The way this actually works is as follows: The compiler program implements, besides our own PWM design, also the design of a logic analyzer. The data from this is sent over the programming port to the computer. The signals on our picture actually represents the signals inside our device. This actually is a very helpful tool to debug our designs. The FPGA in this case is running at full speed, while we can monitor all the signal levels we want inside. In Altera terms, this is called a "Signal Tap". The data collected from our selected lines is stored in the device's internal memory blocks and sent over the JTAG programming port.

	== Shifting <s>reality</s> registers ==		== Shifting <s>reality</s> registers ==

Danny w: /* Shifting reality registers */

2016-01-01T12:01:56Z

Shifting reality registers

← Older revision		Revision as of 15:01, 1 January 2016
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	We are going to use this SPI bus protocol to provide the 8 bits needed for our PWM design.		We are going to use this SPI bus protocol to provide the 8 bits needed for our PWM design.

			<pre>

			library ieee;
			use ieee.std_logic_1164.all;
			use ieee.std_logic_unsigned.all;

			entity spi_pwm is
			port(
			clock : in std_logic;
			pwm_out : out std_logic;

			spi_data : in std_logic;
			spi_clock : in std_logic;
			spi_latch : in std_logic
			);
			end entity spi_pwm;

			architecture behavioural of spi_pwm is

			signal spi_data_latch : std_logic_vector(7 downto 0);
			signal spi_latch_shift : std_logic_vector(1 downto 0);
			signal spi_data_register : std_logic_vector(7 downto 0);

			component pwm_output is
			port(
			pwm_clock : in std_logic;
			pwm_value : in std_logic_vector(7 downto 0);
			pwm_out : out std_logic
			);
			end component pwm_output;

			begin

			spi_shift : process (spi_clock)
			begin
			if spi_clock'event and spi_clock = '1' then
			spi_latch_shift <= spi_latch_shift(0) & spi_latch;
			spi_data_register <= spi_data_register(6 downto 0) & spi_data;
			if spi_latch_shift = "01" then
			spi_data_latch <= spi_data_register;
			end if;
			end if;
			end process spi_shift;

			pwm_process : pwm_output
			port map(
			pwm_clock => clock,
			pwm_value => spi_data_latch,
			pwm_out => pwm_out
			);

			end behavioural;
			</pre>

			Let's take a closer look at <code>spi_latch_shift <= spi_latch_shift(0) & spi_latch;</code>. When a rising edge of spi_clock occurs (from the process declaration), the new value for <code>spi_latch_shift</code> will be: <code>spi_latch_shift(0)</code> and <code>spi_latch</code>. <code>spi_latch_shift</code> is defined as <code>spi_latch_shift(1 downto 0)</code> so the data in <code>spi_latch_shift(0)</code> will become <code>spi_latch_shift(1)</code>. What happens with the old value of <code>spi_latch_shift(1)</code>? it's lost!. We effectively created a history buffer for <code>spi_latch</code>. We know the current value, because it's assigned to <code>spi_latch_shift(0)</code>, and we know what it was a clock cycle before that, in <code>spi_latch_shift(1)</code>. This enables us to see if the latch signal has changed in value. In <code>if spi_latch_shift = "01" then</code> we test if the value has changed from '0' to '1', and if that is the case, we latch the data in <code>spi_data_register</code> into <code>spi_data_latch</code>. <code>spi_data_latch</code> is also a shift register for <code>spi_data</code>, but it is 8 bits wide. We know what the value for <code>spi_data</code> was for 8 clock cycles before, and we use these to fill our <code>spi_data_latch</code>, and ultimately our value for <code>pwm_value</code>.

	[[Category: Project]]		[[Category: Project]]

Danny w: /* Components */

2016-01-01T11:29:28Z

Components

← Older revision		Revision as of 14:29, 1 January 2016
Line 159:		Line 159:

	We start the architecture with our component instantiation. We can "map" the signals and generics inside our component to internal or external signals in our PWM output entity, and fixed values like the binary '0' for our reset signal. We do not want our counter to reset to its 0-state. Instead, the counter will wrap around if we count further than the bit capability. This will represent the PWM cycle in our design. If the current counter value is lower than the desired one in the <code>pwm_value</code> input, the output of our design will be high. Otherwise, the output will be low. For our 8 bit (0 to 255 value) PWM design, a PWM value of 63 will mean a quarter of the period time high, and three quarters of the period time low output value.		We start the architecture with our component instantiation. We can "map" the signals and generics inside our component to internal or external signals in our PWM output entity, and fixed values like the binary '0' for our reset signal. We do not want our counter to reset to its 0-state. Instead, the counter will wrap around if we count further than the bit capability. This will represent the PWM cycle in our design. If the current counter value is lower than the desired one in the <code>pwm_value</code> input, the output of our design will be high. Otherwise, the output will be low. For our 8 bit (0 to 255 value) PWM design, a PWM value of 63 will mean a quarter of the period time high, and three quarters of the period time low output value.

			== Shifting <s>reality</s> registers ==

			Let's take a look at the usability of our PWM design. A single output, but besides from a clock input, we spent 8 inputs on defining a PWM value for our design. If we have multiple PWM designs in an FPGA, or other needs for inputting data, we can very easily surpass the device's pin count. Fortunately, an easy to implement communication protocol exists for inputting data in a serial fashion: the SPI or Serial Peripheral Interconnect bus. The SPI bus consists of a small number of pins: a data pin, clock pin and a latch pin. Communication runs from a master device who generates the clock and latch signals, and a slave device who reacts to these master signals. Data direction can be either or both ways. To be able to communication to multiple slave devices, SPI bus masters can implement a Slave Select pin for each slave, or slave devices can pass through data to another slave (also known as daisy-chaining).

			[[File:daisy_chain.png]]

			We are going to use this SPI bus protocol to provide the 8 bits needed for our PWM design.

	[[Category: Project]]		[[Category: Project]]

Danny w: /* Components */

2016-01-01T10:41:19Z

Components

← Older revision		Revision as of 13:41, 1 January 2016
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	if pwm_clock'event and pwm_clock = '1' then		if pwm_clock'event and pwm_clock = '1' then
	if counter_value <= pwm_value then		if counter_value <= pwm_value then
			pwm_out <= '1';
			else
	pwm_out <= '0';		pwm_out <= '0';
	~~else~~
	~~pwm_out <= '1';~~
	end if;		end if;
	end if;		end if;
Line 155:		Line 155:
	end behavioural;		end behavioural;
	</pre>		</pre>

			In this example, we made an entity, <code>pwm_counter</code>, with some ports. In the architecture of this entity (named behavioural), we defined, apart form a signal, also a component. The name of this component matches our previously made entity <code>counter</code> and the generic and port declaration of this component matches the one of the entity. We now can use this component in our design. One time, but also multiple times, even with a different <code>generic</code> mapping.

			We start the architecture with our component instantiation. We can "map" the signals and generics inside our component to internal or external signals in our PWM output entity, and fixed values like the binary '0' for our reset signal. We do not want our counter to reset to its 0-state. Instead, the counter will wrap around if we count further than the bit capability. This will represent the PWM cycle in our design. If the current counter value is lower than the desired one in the <code>pwm_value</code> input, the output of our design will be high. Otherwise, the output will be low. For our 8 bit (0 to 255 value) PWM design, a PWM value of 63 will mean a quarter of the period time high, and three quarters of the period time low output value.

	[[Category: Project]]		[[Category: Project]]

Danny w: /* Instantiating */

2016-01-01T10:22:42Z

Instantiating

← Older revision		Revision as of 13:22, 1 January 2016
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	There is another thing we can have within the architecture, which can be of good use: A component. A component is an existing entity, which we can use in our current design. Instead of defining every single function again, we can have a hierarchic structure. A lot of simple entity functions can add up to a complex design. Instead of defining a process, we can "port map" a component to existing signals within our design. This is also the way to connect instantiations as well.		There is another thing we can have within the architecture, which can be of good use: A component. A component is an existing entity, which we can use in our current design. Instead of defining every single function again, we can have a hierarchic structure. A lot of simple entity functions can add up to a complex design. Instead of defining a process, we can "port map" a component to existing signals within our design. This is also the way to connect instantiations as well.

	== ~~Instantiating~~ ==		== Components ==

	Now we've built a very usable counter design in VHDL, let's use this to make a more complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?		Now we've built a very usable counter design in VHDL, let's use this to make a more complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?

Danny w: /* Instantiating */

2016-01-01T10:07:55Z

Instantiating

← Older revision		Revision as of 13:07, 1 January 2016
Line 99:		Line 99:
	Now we've built a very usable counter design in VHDL, let's use this to make a more complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?		Now we've built a very usable counter design in VHDL, let's use this to make a more complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?

	At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, ~~out~~ counter design must be a component of our PWM design. Let's look at the code how this is accomplished.		At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, our counter design must be a component of our PWM design. Let's look at the code how this is accomplished.

	<pre>		<pre>

Danny w: /* Instantiating */

2016-01-01T10:07:04Z

Instantiating

← Older revision		Revision as of 13:07, 1 January 2016
Line 97:		Line 97:
	== Instantiating ==		== Instantiating ==

	Now we've built a very usable counter design in VHDL, let's use this to make a ~~core~~ complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?		Now we've built a very usable counter design in VHDL, let's use this to make a more complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?

	At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, out counter design must be a component of our PWM design. Let's look at the code how this is accomplished.		At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, out counter design must be a component of our PWM design. Let's look at the code how this is accomplished.

Danny w: /* Instantiating */

2016-01-01T10:05:42Z

Instantiating

← Older revision		Revision as of 13:05, 1 January 2016
Line 100:		Line 100:

	At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, out counter design must be a component of our PWM design. Let's look at the code how this is accomplished.		At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, out counter design must be a component of our PWM design. Let's look at the code how this is accomplished.

			<pre>
			library ieee;
			use ieee.std_logic_1164.all;
			use ieee.std_logic_unsigned.all;

			entity pwm_output is
			port(
			pwm_clock : in std_logic;
			pwm_value: in std_logic_vector(7 downto 0);

			pwm_out : out std_logic
			);
			end entity pwm_output;

			architecture behavioural of pwm_output is

			signal counter_value : std_logic_vector(7 downto 0);

			component counter is
			generic(
			counter_width : natural
			);
			port(
			clock : in std_logic;
			reset : in std_logic;
			count : out std_logic_vector(counter_width-1 downto 0)
			);
			end component counter;

			begin

			pwm_counter : counter
			generic map(
			counter_width => 8
			)
			port map(
			clock => pwm_clock,
			reset => '0',
			count => counter_value
			);

			pwm_compare : process (pwm_clock)
			begin
			if pwm_clock'event and pwm_clock = '1' then
			if counter_value <= pwm_value then
			pwm_out <= '0';
			else
			pwm_out <= '1';
			end if;
			end if;
			end process pwm_compare;

			end behavioural;
			</pre>

	[[Category: Project]]		[[Category: Project]]

Danny w at 09:43, 1 January 2016

2016-01-01T09:43:43Z

← Older revision		Revision as of 12:43, 1 January 2016
Line 94:		Line 94:

	There is another thing we can have within the architecture, which can be of good use: A component. A component is an existing entity, which we can use in our current design. Instead of defining every single function again, we can have a hierarchic structure. A lot of simple entity functions can add up to a complex design. Instead of defining a process, we can "port map" a component to existing signals within our design. This is also the way to connect instantiations as well.		There is another thing we can have within the architecture, which can be of good use: A component. A component is an existing entity, which we can use in our current design. Instead of defining every single function again, we can have a hierarchic structure. A lot of simple entity functions can add up to a complex design. Instead of defining a process, we can "port map" a component to existing signals within our design. This is also the way to connect instantiations as well.

			== Instantiating ==

			Now we've built a very usable counter design in VHDL, let's use this to make a core complex design. A PWM output is a single digital output to represent multiple values. Besides 0% on and 100% on, being a low signal level and a high signal level, we can assign a number of different values to this output. 50% on means that we toggle between low and high in an equally amount of time. 25% means we have 3 times as much low signal level then we have a high signal level. How can we make this in VHDL?

			At some point in out design, we have to compare one value to another. The output of this comparison is the output of our PWM design. If we hold the desired PWM value in a register, we have to have a mechanism that steps through all possible values. If we compare these two values, we have built ourselves a PWM output!. The simplest way to step through a range of values is a counter. Let's use our previously built counter for this purpose. To do that, out counter design must be a component of our PWM design. Let's look at the code how this is accomplished.

	[[Category: Project]]		[[Category: Project]]